1. Field of the Invention
The present invention relates to a semiconductor memory device and manufacturing method. More particularly, the present invention relates to a SONOS memory device with enhanced thermal stability and a method of manufacturing the same.
2. Description of the Related Art
A unit memory cell in a semiconductor memory device, e.g., a dynamic random access memory (DRAM), includes one transistor and one capacitor. Therefore, the size of a transistor and/or a capacitor should be reduced in order to enhance a degree of integration.
In a manufacturing process for an early semiconductor memory device, a photo and etching process provided a sufficient process margin. Thus, the degree of integration was not important. In addition, the degree of integration was enhanced to some extent by reducing the size of other components forming the semiconductor memory device.
However, as the demand for semiconductor memory devices having a high degree of integration has increased, a new method to enhance the degree of integration in semiconductor memory devices has been required.
The degree of integration of a semiconductor memory device is directly related to a design rule. Thus, since the design rule has to be more strictly maintained in order to enhance the degree of integration, the margin of the photo and etching process may be very narrow. Accordingly, the photo and etching process has to be more accurately performed.
The narrow margin of the photo and etching process results in low yield. Thus, a new method not only for enhancing the degree of integration, but also for preventing low yield, has been required.
A semiconductor memory device that addresses this problem has a totally different structure from a conventional one. More specifically, it has a data storing medium above a transistor, such as a giant magneto-resistance (GMR) or tunneling magneto-resistance (TMR) medium, which performs different storing operations than a conventional capacitor.
A silicon oxide nitride oxide silicon (SONOS) memory device is one of these semiconductor memory devices. FIG. 1 illustrates a cross-sectional view of a conventional SONOS memory device (hereinafter, “the conventional memory device”).
Referring to FIG. 1, the conventional memory device includes a p-type substrate 10 (hereinafter, “the substrate”) having a source area 12 in which n-type conductive impurities are injected, a drain area 14, and a channel area 16 formed between the source and drain areas 12 and 14. A gate stack material 30 is formed on the channel area 16 of the substrate 10. The gate stack material 30 is formed by sequentially stacking a tunneling oxide layer 18, a silicon nitride (Si3N4) layer 20, a blocking oxide layer 22, and a gate electrode 24. Here, the tunneling oxide layer 18 and the blocking oxide layer 22 are silicon oxide (SiO2). The tunneling oxide layer 18 comes in contact with the source and drain areas 12 and 14. The Si3N4 layer 20 has a trap site having a predetermined density. Therefore, when a predetermined voltage is applied to the gate electrode 24, electrons which pass through the tunneling oxide layer 18 are trapped in the trap site of the Si3N4 layer 20. The blocking oxide layer 22 blocks electrons from moving to the gate electrode 24 when the electrons are trapped in the trap site of the Si3N4 layer 20.
The conventional memory device has a different threshold voltage depending on whether the electrons are trapped in the trap site of the Si3N4 layer 20. By using this feature, the conventional memory device can save and read information. However, the conventional memory device not only has a long data erasing time, but also has a short retention time, i.e., a time during which saved data is properly maintained.
To solve the above problems, a SONOS memory device in which the Si3N4 layer 20, i.e., a trapping layer, is replaced with a hafnium oxide (HfO2) layer having high permittivity and the blocking layer 22 is replaced with an aluminum oxide (Al2O3) layer, has been suggested.
However, while a crystallization temperature of most of a metal oxide layer having high permittivity is 700° C.˜800° C., a temperature of general metal oxide semiconductor (MOS) processes, e.g., a process to activate conductive impurities which are injected into the source and drain areas 12 and 14, is over 900° C. Given this fact, when the Si3N4 layer 20 and the blocking oxide layer 22 are replaced with metal oxide layers having high permittivity, it is not possible to prevent the crystallization of these metal oxide layers during general MOS processes. This crystallization of metal oxide layers having high permittivity presents the following problems.
First, the surface roughness of a trapping layer of crystallized metal oxide is large. Thus, an effective distance between the metal oxide layers used as the trapping layer and the blocking oxide layer is not constant. This degrades a retention characteristic.
Second, the density of the trap site of the trapping layer is highest when the trapping layer is in an amorphous substance. However, if the trapping layer is crystallized, the density of the trap site of the trapping layer is lowered and the characteristic of the trapping layer serving as a memory node layer is degraded.
Third, materials forming the metal oxide layer having high permittivity used as the trapping layer, e.g., a HfO2 layer, and used as the blocking oxide layer, e.g., an Al2O3 layer, are mixed together during general MOS processing at temperatures over 900° C. As a result, it is difficult to distinguish boundaries between the trapping and blocking layers.
Fourth, thermal instability occurs. This thermal instability can be seen by referring to FIG. 2. FIG. 2 is a graph illustrating a problem in a SONOS memory device including a metal oxide (MO) stack for low voltage operations, which is suggested as an alternative to the SONOS memory device of FIG. 1
Referring to FIG. 2, the first graph G1 illustrates a current-voltage characteristic shortly after sequentially forming HfO2 and Al2O3 layers on a tunneling oxide layer, which is still a SiO2 layer. The second graph G2 illustrates a current-voltage characteristic measured after sequentially forming the HfO2 and Al2O3 layers on the tunneling oxide layer and annealing these layers at a temperature of 900° C. That is, the first graph G1 shows the current-voltage characteristic before the crystallization of the HfO2 and Al2O3 layers and the second graph G2 shows the current-voltage characteristic after the crystallization of the HfO2 and Al2O3 layers.
Comparing the first and second graphs G1 and G2, the current-voltage characteristics before and after the crystallization of the HfO2 and Al2O3 layers are different. Particularly, the first graph G1 is greatly distorted as a gate voltage Vg approaches 1V, while the second graph G2 is much less so. These differences arise because thermal stability before and after the crystallization is not guaranteed.